IP Catalog > Processor IP > General Purpose Processor IP > RISC-V Processor IP > 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)

32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)

Overview

The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructions, and “N” for user-level interrupts. It is capable of delivering high performance and operating at high frequency and high performance. D45 is also equipped with comprehensive SIMD/DSP instructions that can boost the performance of voice, audio, image and signal processing. Its “FD” extensions support IEEE754-compliance single and double precision floating point instructions as well. It incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. In addition, D45 features advanced low power branch prediction mechanism for efficient branch execution, instruction and data caches, local memories, and ECC error protection. It also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 64-bit bus, rich power management, and JTAG debug and trace interface for software development support.

Key Features

  • CPU Core
    • 8-stage in-order dual issue pipeline with a full-cycle reserved for critical SRAM accesses
    • AndeStar™ V5 32-bit architecture
      • V5 state-of-the-art ISA. Little endian
      • RISC-V RV32IMACN support.
      • RISC-V P-extension (draft) DSP/SIMD instructions with versatile operations (see DSP summary for details)
      • RISC-V F and D single/double-precision floating point
      • Machine(M), User(U) privileges, and Supervisor(S) privileges
    • Multiplier options of pipelined 2-cycle multiplier or multiplier producing 1, 2, 4, or 8 bits per cycle
    • Optional Advanced Dynamic Branch Prediction
      • Branch Target Buffer (BTB)
      • Branch History Table (BHT)
      • Return Address Stack (RAS)
    • Memory Subsystem
      • Instruction and Data Cache
        • Separately configurable from 8KB up to 64KB
        • Direct-mapped, 2-way or 4-way set associate
        • Support instruction and data cache lock
        • Optional Parity or ECC error protection
      • Instruction and Data Local Memory (ILM & DLM)
        • Separately configurable from 4KB up to 16MB
        • SRAM interface support
        • Optional Parity or ECC error protection
        • Slave port accesses from bus masters
      • MemBoost - Enhanced Memory Performance
        • Data cache write-around
        • Instruction and data prefetch
        • Up to 8 read, 8 write outstanding bus requests
      • Bus Interfaces
        • AXI bus master port
          • 64-bit data bus, I/D joint or separate bus
        • Synchronous N:1 core vs. bus clock ratios
      • Power Management
        • PowerBrake technology to reduce peak power consumption
        • QuickNap™ for logic power-down and SRAM in retention
        • WFI (Wait for Interrupt) instruction for software controlled stalls
      • Platform-Level Interrupt Controller (PLIC)
        • Up to 1023 interrupt sources, up to 255 interrupt priority levels, and up to 16 interrupt targets
        • Enhanced Interrupt Features
          • Vectored interrupt dispatch
          • Priority-based preemption
          • Selectable edge trigger or level trigger
        • Trace Encoder Interface
          • Optional Instruction Trace
        • External Debug Module
          • Secure Debug
          • JTAG debug interface, up to 8 triggers
          • Exception redirection handling

        Benefits

        • Performance
          • 32-bit in-order dual-issue 8-stage pipeline CPU architecture
          • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
          • DSP/SIMD extensions
          • Floating point extensions
          • Andes extensions, architected for performance and functionality enhancements
          • 16/32-bit mixable instruction format for compacting code density
          • Advanced low power branch predication to speed up control code
          • Return Address Stack (RAS) to accelerate procedure returns
          • Physical Memory Protection (PMP), and programmable Physical Memory Attribute (PMA)
          • MemBoost for heavy memory transactions
          • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
          • Enhancement of vectored interrupt handling for real-time performance
          • Advanced CoDense™ technology to reduce program code size
        • Flexibility
          • Easy arrangement of preemptive interrupts
          • StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
          • ECC or Parity check on level-one memories for fault protection
          • Several configurations to tradeoff between core size and performance requirements
        • Power Management
          • PowerBrake, QuickNap™ and WFI (Wait For Interrupt) for power management at different occasions

        Block Diagram

        32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP) Block Diagram

        Applications

        • Networking and Communications
        • Advanced Driver-Assistance Systems
        • Video and Image Processing
        • Smart wireless switch/router
        • Machine/Deep Learning acceleration

        Deliverables

        • AndesCore™ D45 Single-core Processor with AE350 AXI Platform
          • Pre-integrated D45 single-core CPU subsystem, PLIC, Debug Module, and AXI Platform

        Technical Specifications

        Maturity
        MP
        Availability
        Now
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