IP Catalog > Processor IP > General Purpose Processor IP > RISC-V Processor IP > 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN

32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN

Overview

The 32-bit N45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, and “N” for user-level interrupts. It issues two instructions per cycle that significantly increases the performance efficiency that is important for many applications. Its “FD” extensions support IEEE754-compliance single and double precision floating point instructions as well. It incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. In addition, N45 features advanced low power branch prediction mechanism for efficient branch execution, instruction and data caches, local memories, and ECC error protection. It also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 64-bit bus, rich power management, and JTAG debug and trace interface for software development support.

Key Features

  • CPU Core
    • 8-stage in-order dual issue pipeline with a full-cycle reserved for critical SRAM accesses
    • AndeStar™ V5 32-bit architecture
      • V5 state-of-the-art ISA. Little endian
      • RISC-V RV32IMACN support.
      • RISC-V F and D single/double-precision floating point
      • Machine(M), User(U) and optional Supervisor(S) privileges
      • PMP and PMA with up to 16 regions
    • Multiplier options of pipelined 2-cycle multiplier or multiplier producing 1, 2, 4, or 8 bits per cycle
    • Advanced Dynamic Branch Prediction
      • Branch Target Buffer (BTB)
      • Branch History Table (BHT)
      • Return Address Stack (RAS)
    • Memory Subsystem
      • Instruction and Data Cache
        • Individually configurable from 8KB up to 64KB
        • Direct-mapped, 2-way or 4-way set associate
        • Support instruction and data cache lock
        • Optional Parity or ECC error protection
      • Instruction and Data Local Memory (ILM & DLM)
        • Individually configurable from 4KB up to 16MB
        • SRAM interface support
        • Optional Parity or ECC error protection
        • Slave port accesses from bus masters
      • MemBoost - Enhanced Memory Performance
        • Data cache write-around
        • Instruction and data prefetch
        • Up to 8 read, 8 write outstanding bus requests
      • Bus Interfaces
        • AXI bus master port
          • 64-bit width data width, I/D joint or separate bus
        • Synchronous N:1 core vs. bus clock ratios
      • Power Management
        • PowerBrake technology to reduce peak power consumption
        • QuickNap™ for fast logic power-down with SRAM in retention mode
        • WFI (Wait for Interrupt) instruction for software controlled stalls
      • Platform-Level Interrupt Controller (PLIC)
        • Up to 1023 PLIC interrupt sources, up to 255 PLIC interrupt priority levels, and up to 16 PLIC interrupt targets
        • Enhanced Interrupt Features
          • Vectored interrupt dispatch
          • Priority-based preemption
          • Selectable edge trigger or level trigger
        • Trace Encoder Interface
          • Optional Instruction Trace
        • External Debug Module
          • Secure debug
          • JTAG debug interface with up to 8 triggers
          • Exception redirection handling

        Benefits

        • Performance
          • 32-bit in-order dual-issue 8-stage pipeline CPU architecture
          • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
          • IEEE754-compliance single and double precision floating point extensions
          • Andes extensions, architected for performance and functionality enhancements
          • 16/32-bit mixable instruction format for compacting code density
          • Advanced low power branch predication to speed up control code, and Return Address Stack (RAS) to accelerate procedure returns
          • Physical Memory Protection (PMP) , and Physical Memory Attribute (PMA)
          • MemBoost for heavy memory transactions
          • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
          • Enhancement of vectored interrupt handling for real-time performance
          • Advanced CoDense™ technology to further reduce code size on top of “C” extension
        • Flexibility
          • Easy arrangement of preemptive interrupts
          • StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
          • ECC or Parity check on level-one memories for fault protection
          • Several configurations to tradeoff between core size and performance requirements
        • Power Management
          • PowerBrake, QuickNap™ and WFI (Wait For Interrupt) for power management at different occasions

        Block Diagram

        32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN Block Diagram

        Applications

        • Networking and Communications
        • Advanced Driver-Assistance Systems
        • Video and Image Processing
        • Smart wireless switch/router
        • Machine/Deep Learning acceleration

        Deliverables

        • AndesCore™ N45 Single-core Processor with AE350 Platform– pre-integrated RTL with CPU subsystem (including PLIC, Debug Module) and AXI Platform

        Technical Specifications

        Maturity
        MP
        Availability
        Now
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