32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux

The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP (draft) instructions, “B” bit manipulation, and Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions. It features MMU for Linux based applications, dynamic branch prediction for efficient branch execution, dual-issue of common instruction pairs, instruction and data caches and local memories for low-latency accesses. A45 equipped with comprehensive SIMD/DSP instructions that can boost the performance of voice, audio, image and signal processing. Its ”B” extensions provide some combination of code size reduction, performance improvement, and energy reduction, and “FD” extensions support IEEE754-compliance single and double precision floating point instructions. A45 incorporates MemBoost to enhance memory bandwidth and reduce memory latencies for intensive memory accesses. Other features include ECC for memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™ for software quality improvement, PowerBrake and WFI for power management.