32-bit SPARC V8 processor

Overview

Key Features

• SPARC V8 instruction set with V8e extensions
• Advanced 7-stage pipelineHardware multiply, divide and MAC units
• Hardware floating-point support
• Separate instruction and data cache (Harvard architecture) with snooping
• Configurable caches: 1 - 4 ways, 1 - 256 kbytes/way. Random, LRR or LRU replacement
• Local instruction and data scratchpad RAM, 1 - 512 Kbytes
• AMBA 2.0 AHB bus interface
• High Performance: 1.4 DMIPS/MHz, 1.8 CoreMark/MHz (gcc -4.1.2)
• Advanced on-chip debug support with instruction and data trace buffer
• SPARC Reference MMU (SRMMU) with configurable TLBSymmetric Multi-processor support (SMP)
• Power-down mode and clock gating
• Robust and fully synchronous single-edge clock design
• Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
• Fault-tolerant and SEU-proof version available for space applications
• Extensively configurable
• Large range of software tools: compilers, kernels, simulators and debug monitors

Benefits

• Low cost license fee
• Easily prototyped on low-cost FPGA boards
• SPARC V8 conformant
• High performance (400 MHz 0.13 ASIC, 100 MHz FPGA)
• Low area (30 - 50 Kgates, 5 - 10,000 LUTs)

Block Diagram

Deliverables

• Fully synthesisable VHDL code
• VHDL test bench
• Ducumentation
• Synthesis scripts
• Place&route scripts for FPGA boards
• GNU-based Cross-compiler
• High-performance behavioural simulator
• Technical support

Technical Specifications