FPD-link, 30-Bit Color LVDS Receiver, 20-112Mhz

Overview

V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.

This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals).

At a maximum pixel rate of 112Mhz, LVDS data line speed is 784Mbps, providing a total maximum bandwidth of 3.92Gb/s (490Mbytes per second).

Four (4) instances can provide FullHD @ 120Hz (3DTV)

Key Features

1P7M/1P8M/1P9M/1P10M layout structure based on 65nm Logic 1P10M Salicide 1.2V/2.5V process.
1.2V/2.5V ±10% supply voltage, -40/+125°C
Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
Up to 3.92Gbps bandwidth (20 to 112Mhz pixel clock)
Input clock detector (self reset when missing clock)
Low bounding pad count
Spread-spectrum input clock support (can be used in SS systems)
Core cell area : [contact us]
Current consumption [contact us] @ 75Mhz
Built-in power pads with ESD protection.
Low leakage power-down mode <1uA.

Benefits

Lowest bounding pad count
Low cost IP
reliability
highly adjustable
customization for your own design

Deliverables

Design kit includes :

LEF view and abstract gdsII
Verilog HDL behavioral model

Liberty (.lib) timing constraints for typical, worse and best corner case

Full Datasheet /Application Note with integration guidelines document
Silicon characterization report when available

Tapeout kit includes the design kit plus plysical view:

gdsII
LVS netlist and report
DRC/ERC/ESD/ANT report

Technical Specifications

Availability

SMIC

Pre-Silicon: 65nm LL

TSMC

Pre-Silicon: 65nm G , 65nm GP , 65nm LP

UMC

Pre-Silicon: 65nm LL , 65nm LP , 65nm SP

Request Info