Fast sort IP core

Overview

The Fast sort IP core is a AXI-compatible digital hardware block with internal data sorting algorithm. Hardware implementation of a sorting algorithm reduces complexity of a software data processing, data sorting time and increases performance in time-critical applications. The Fast sort IP core can be used for sorting custom data, sorting array of data structure and for nonlinear filters such as a median filter, minmax filter or a rank's filter.
The Fast sort IP core require low hardware resources and has a high maximum clock frequency. In real cases The Fast sort IP core can increase a sorting time up to 10-20 times.

Key Features

Special sorting block for hardware implementation
Low resources requirements
One clock signal requirements
Sorted array on each clock cycle
AXI4-Lite compatible interface
Programmable register for various sorting modes
Programmable rank display mode
Used only FUT and FF resources
Clock frequency over 300 MHz for 128 data points

Benefits

Sorting speed increasing
Linear sorting time
Code simplification
Simple integration and using

Applications

Machine vision
Machine learning
IoT
Flash controllers
Logical controllers
Time-critical application
Digital signal processing
RF systems

Deliverables

Netlist of The Fast sort IP core with fixed synthesized parameters;
The verification environment for The Fast sort IP core netlist modeling and testing;
Test project for The Xilinx Vivado® for Zync-7000 SoC;
HAL on C language for standalone embedded application;
Driver of Linux OS for The Fast sort IP core data exchange;
User manual and technical documentation.

Technical Specifications

Maturity

release

Availability

in stock

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