DTI I3C Controller provides the logic consistent with NXP I3C specification to support the communication of low-speed integrated circuits through I3C bus.
The IP facilitates software controllable by application processor through industry-standard AMBA interface. The bus interface is flexible and easily integrated into APB, AHB or AXI system bus.
Dolphin I3C Controller & PHY
Overview
Key Features
- DTI I3C Controller supports:
- + Two wire serial interface up to 12.5 MHz using Push-Pull
- + Legacy I2C Device co-existence on the same Bus (with some limitations)
- + Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
- + Legacy I2C messaging
- + I2C-like Single Data Rate Messaging (SDR)
- + Optional High Data Rate Messaging Modes (HDR-DDR, HDR-TSL, HDR-TSP)
- + Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present)
- + Reception of In-band Interrupt Support from the I3C Slave devices
- + Reception of Hot-Join from newly added I3C Slave devices
- + Synchronous Timing Support and Asynchronous Time Stamping
- + Master only operation
- + Slave only operation
- + Master and slave operation
- DTI I3C Master supports:
- + Transmission modes: Single Data Rate (SDR) Mode
- + Dynamic Address Assignment
- + Host-join request
- + Secondary master request to be current master
- + Slave interrupt request
- + Support for I3C common command codes
- + Error Detection and Recovery Methods for SDR
- DTI I3C Slave supports:
- + Transmission modes: Single Data Rate (SDR) Mode
- + Dynamic Address Assignment
- + Host-join
- + In-Band Interrupt
- + Error Detection and Recovery Methods for SDR
- + Detect HDR Exit Pattern
- + Support for I3C common command codes:
- - Broadcast CCCs: RSTDAA, ENTDAA, ENEC, DISEC, ENTAS0, ENTAS1, ENTAS2, ENTAS3, SETMWL, SETMRL
- - Direct CCCs: SETDASA, SETNEWDA, GETSTATUS, ENEC, DISEC, ENTAS0, ENTAS1, ENTAS2, ENTAS3, SETMWL, SETMRL, GETMWL, GETMRL, GETMXDS, GETPID, GETBCR, GETDCR, GETXTIME
Benefits
- Compliant with the following specifications:
- + MIPI I3C specification v1.0
- + AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
- + AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
- + AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
- + AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Applications
- Communications, Data Processing, Industrial, Automotive
Deliverables
- Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- Synthesis and STA scripts
- User guide documents
- SV/UVM Verification suite with BFM
Technical Specifications
Maturity
Pre Silicon
Availability
Yes