How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SkyeChip
Category:
DDR
DDR5/4 PHY & Controller
High performance, low power and area efficient memory interface solutions conforming to DDR5 (JESD79-5) and DDR4 (JESD79-4) JEDEC…
Overview
High performance, low power and area efficient memory interface solutions conforming to DDR5 (JESD79-5) and DDR4 (JESD79-4) JEDEC standards
Key features
- One stop PHY & Controller solution with an average random efficiency of more than 85%
- Supports up to 4800 MT/s rates with upgradable option to 6400 MT/s
- DFI 5.0 compliant interface to the memory controller
- I/Os include receiver decision feedback equalization (DFE) and transmitter feed forward equalization (FFE)
- Flexible PHY with programmable intelligent interface training sequences
- Supports x4, x8 and x16 SDRAMs
- Supports up to 64Gb addressing for DDR5 and up to 32Gb addressing for DDR4
- Supports 3DS extensions up to 16H for DDR5 and up to 8H for DDR4
- Supports up to 4 ranks for components, UDIMM, RDIMM and LRDIMM
- Add-on features/engines for MPFE, RAS, Ping-Pong and Debug available upon request
Specifications
Identity
Part Number
DDR5/4 PHY & Controller
Vendor
SkyeChip
Provider
SkyeChip
HQ:
Malaysia
SkyeChip is a Malaysia based design company dedicated to deliver cutting edge IP & IC solutions for artificial intelligence and high-performance computing. The company is founded in 2019 by a group of world class IC designers with average experience of more than 15 years in MNCs including Intel, Altera, Broadcom, Spansion, Motorola, etc.
SkyeChip has in-depth and complete technical expertise to develop advanced IP and ASIC products, including architecture, micro-architecture, logic design, circuit design, DFT, physical design, layout, test and product engineering. In addition, the SkyeChip team also has extensive experience in project management, new product introduction, and management of global supply chain for volume production.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
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DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
Which DDR SDRAM Memory to Use and When
This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
DDR5/4/3/2: How Memory Density and Speed Increased with each Generation of DDR
Frequently asked questions about DDR Controller IP cores
What is DDR5/4 PHY & Controller?
DDR5/4 PHY & Controller is a DDR IP core from SkyeChip listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.