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MIPI I3C IP

MIPI I3C® IP is a scalable, medium-speed, utility and control bus interface for connecting peripherals to an application processor, streamlining integration and improving cost efficiencies. It gives developers unprecedented opportunities to craft innovative designs for any mobile product—from smartphones, to wearables, to systems in automobiles.

Designed as the successor of I2C, MIPI I3C incorporates key attributes of the traditional I2C and SPI interfaces to provide a unified, high-performing, very-low-power solution and delivers a robust, flexible upgrade path to I3C for I2C and SPI implementers. While I3C v1.0 delivered new capabilities to integrate mechanical, motion, biometric, environmental and any other type of sensor, updates to the specification have added new features for peripheral command, control and communication to a host processor over a short distance and system manageability.

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Search (62)
Compare 62 MIPI I3C IP from 17 vendors (1 - 10)
  • MIPI I3C Master RISC-V based subsystem
    • RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interface for sensors
    • All the basic functionalities of MIPI I3C master has been proved with Microsemi smart fusion 2 creative development board .In addition the MIPI I3C master supports for both AHB lite and APB Interface
    Block Diagram -- MIPI I3C Master RISC-V based subsystem
  • Temperature Sensor
    • The TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus
    • These device operate on I2C and I3C two wire serial bus interface
    • The TS5 designed for Memory Module Applications
    • The TS5 device intended to operate up to 12.5 MHz on a I3C Basic Bus or up to 1 MHz on a I2C Bus
    • All TS5 devices respond to specific pre-defined device select code on the I2C/I3C Bus
    Block Diagram -- Temperature Sensor
  • ETSI SSP I3C Interface
    • The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Common Layer (SCL) protocol
    • The use of the MIPI I3C Basic bus specification provides the ETSI SSP with a multitude of benefits, such as higher data rate, flexible and efficient information exchange, and strong integration of SSP in connected devices
    Block Diagram -- ETSI SSP I3C Interface
  • MIPI-I3C UVM VIP
    • The MIPI-I3C VIP provides configurable option to select I3C master/secondary master/slave based on the MIPI I3C DUT function as per user specification
    • Our VIP supports both Single Data Rate (SDR) and High Data Rate (HDR) mode operations
    • Our VIP has a Bus Monitor for performing all protocol checks via assertion and functional coverage option
    • The monitor also performs key protocol checks and reports errors for non compliance with Specification
    Block Diagram -- MIPI-I3C UVM VIP
  • Power Management IC - I3C Basic Interface IP
    • Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application
    • PMIC is used for switching and LDO regulators
    • PMIC-I3C Interface used to select suitable power fit for various application environment
    • PMIC device is intended to operate up to 12.5MHz
    Block Diagram -- Power Management IC - I3C Basic Interface IP
  • MIPI-I3C Slave (SDR) RTL Design IP
    • MIPI I3C slave Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs)
    • The MIPI I3C slave Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system
    Block Diagram -- MIPI-I3C Slave (SDR) RTL Design IP
  • MIPI-I3C Master (SDR) RTL Design IP
    • MIPI I3C master Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs)
    • The MIPI I3C master Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system The MIPI I3C master Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus
    Block Diagram -- MIPI-I3C Master (SDR) RTL Design IP
  • MIPI I3C Basic Slave Controller
    • MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication
    • The MIPI I3C interface has been developed to ease sensor system design architectures in mobile sensor and IoT / automotive sensor wireless products by providing a fast, low cost, low power
    Block Diagram -- MIPI I3C Basic Slave Controller
  • MIPI I3C Basic Master Controller
    • MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication
    • The MIPI I3C interface has been developed to ease sensor system design architectures in mobile sensor and IoT / automotive sensor wireless products by providing a fast, low cost, low power
    Block Diagram -- MIPI I3C Basic Master Controller
  • MIPI I3C Controller Host/Target IP
    • MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs)
    • The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system
    Block Diagram -- MIPI I3C Controller Host/Target IP
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