The AXI DDR3 Controller provides access to DDR3 memory. It accepts the Read / Write commands from AXI and converts it into DDR3 access. While doing this it combines AXI burst transactions into single DDR access where ever possible to achieve the best possible performance from DDR3 memory subsystem.
DDR3 Controller IP
Overview
Key Features
- High memory throughput achieved via Parallel operation of all the banks and reordering of commands in the controller to ensure the maximum utilization of the DDR Memory
- Pipelined operation across the complete design to ensure the highest performance
- DDR Interface
- Supports all standard DDR3 (x4,x8,x16) SDRAMs
- Supports power down modes
- Run-time configurable timing parameters and memory settings
- Automatic generation of initialization and refresh sequences
- All burst lengths (4 & 8) supported
- AXI Interface
- Supports AMBA 3 AXI protocol 32 bit Data Width
- Does re-mapping/combines the AXI Burst transactions into memory transactions by understanding the memory architecture
- Supports unaligned transactions
- Supports multiple outstanding transactions
- Supports delayed Writes(Independent AXI command and Data Channel )
Deliverables
- Verilog RTL/Synchronous Design
- Test Plan, Test Bench ,Test Cases & Test Results
- Architecture Doc & LLD of Individual Blocks
- ISE & DC Synthesis Scripts
Technical Specifications
Foundry, Node
90nm
Maturity
Soft Core
Availability
Now
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