Ethernet TSN Endstation Controller IP for Automotive

Overview

Comprehensive hardware and software TSN capable solution designed for automotive applications

The Ethernet TSN Endstation Controller IP version is envisioned for demanding automotive applications like Advanced Driver-Assistance Systems (ADAS) and autonomous driving with sensors and actuators such as cameras, radars, breaks and steering motors. These applications demand high bandwidth, reliable and secure real-time communication as well as high precision time synchronization.  This version supports 10M/100M/1G/2.5G operation and utilizes standard GMII/RGMII/SGMII and MDIO interfaces to communicate with Ethernet Physical layer devices. Its configuration and status register are accessible via a 32bit AXI4-lite bus.

It also includes a multichannel high-performance DMA controller to transfer packets between the network interface and a host processor system. The DMA controller is connected to the host processor system via a memory mapped AXI4 master port.

The Ethernet TSN Endstation Controller IP family from is a comprehensive hardware and software solution for automotive applications.  The solution implements Timing & Synchronization (802.1AS), Multiple types of Traffic Shaping (802.1Qav, 802.1Qby, 802.1Qcr), Frame preemption (802.1Qbu), Frame replication & elimination (802.1CB), Steam filtering & policing (802.1Qci), and optional MACsec encryption/decryption (802.1AE).

The solution is designed to provide high-precision time synchronization and accurate traffic scheduling. It supports up to 8 traffic classes, each with a dedicated queue for all ports. It is available in two versions: Ethernet TSN Endstation Controller IP and Ethernet Tiny TSN Endstation Controller IP.

Both versions of the Ethernet TSN Endstation controller IP include a comprehensive software package with device drivers for several operating systems, a software stack for 802.1AS and a complete demonstration system based on Linux.

The solution is available as technology independent RTL source code (System Verilog) or encrypted netlist for ASIC and FPGA implementations. Furthermore, FPGA based hardware platforms are available for evaluation and prototyping.

Key Features

  • Versatile Solution
    •  Fully integrated hardware and software solution
    •  One physical Ethernet port and dedicated host port
    • Seamless integration with host CPU or external micro-controller   
    • 10M/100M/1G/2.5G version:
      • DMA engine with dedicated channels for RX/TX with AXI-MM interface
      • GMII/RGMII/SGMII Ethernet physical layer transceiver support
    • 10M/100M version:
      • Dedicated RX/TX host buffer for packet storage with QSPI
      • MII/RMII Ethernet physical layer transceiver support
  • Robust Design
    • Time synchronization as per IEEE 802.1AS with grandmaster and slave support
    • Traffic scheduling as per IEEE 802.1Qav and IEEE 802.1Qbv
    • Frame preemption as per IEEE 802.1Qbu
    • Supports up to 8 traffic classes per port
    • Stream filtering & policing as per IEEE 802.1Qci
  • Optional Features
    •  MACsec encryption/decryption as per IEEE 802.1AE
    •  Asynchronous traffic scheduling as per IEEE 802.1Qcr
    •  Frame replication & elimination as per IEEE 802.1CB
  • Silicon Agnostic
    • Designed in SystemVerilog and targeting both ASICs and FPGAs

Block Diagram

Ethernet  TSN Endstation Controller IP for Automotive Block Diagram

Deliverables

  • IP in SystemVerilog, Source code or Encrypted RTL
  • Comprehensive documentation, including User Manual, Release Note and Product Brief.
  • Simulation Environment, including basic test environment, test cases and test scripts.
  • Software demo application, Complete Linux system with
    • Full integration into Linux
    •  Netconf for configuration & management
  • Software drivers, C code, Linux device driver, FreeRTOS driver
  • IEEE 802.1AS software stack, C code
  • Demo: Complete example design targeted AMD/Xilinx ZCU102 hardware platform, with other hardware platforms on request
  • Access to support system and direct support from Comcores Engineers.
  • Timing Constraints in Synopsys SDC format (optional).
  • Synopsys Lint (optional).
  • Synopsys Lint waiver (optional).

Technical Specifications

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Semiconductor IP