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CAN XL Controller IP

Overview

The CAN XL IP represents a breakthrough, bridging the gap between CAN FD and 100Mbit Ethernet. Supporting data rates up to 20 Mbit/s and data fields up to 2048 bytes, it surpasses previous standards. It also offers flexibility with higher layer protocols and Ethernet frame tunneling.

Maintaining the reliability of the CAN protocol, this solution integrates seamlessly while meeting evolving needs. It is backward compatible with Classical CAN, CAN FD, and CAN XL. External transceiver hardware is required for physical connectivity, with CAN transceivers for bitrates below 10Mbps and CAN SIC XL transceivers for higher bitrates.

CAN XL implementation includes a single or dual-ported Message RAM and integrates with the host CPU via a 32-bit Generic Interface, compatible with popular interface wrappers.

Available in Basic and Safety-Enhanced versions, the latter is developed as an ISO26262-10 Safety Element out of Context with necessary safety mechanisms and documentation. Third-party audits ensure compliance with ASIL-B requirements. Comprehensive FMEDA analysis is provided for integration and system-level safety analysis, making it suitable for Automotive Safety Systems and higher ASIL level readiness.

Key Features

  • Designed in accordance with ISO 11898- 1:2024 specification (tbc) and CiA610-1 specification
  • Supports CAN, CAN FD and CAN-XL frames
  • Supports up to 64 bytes CAN FD frame and up to 2048 bytes CAN-XL data frame
  • Flexible data rates supported
  • AUTOSAR and SAE J1939 support
  • Simple 8/16/32-bit CPU slave interface
  • Data rate up to 1Mbps in Classic CAN mode, up to 8Mbps in FD mode, up to 20Mbps in XL mode
  • Optional PWM coding allows bit-rates of 10 Mbit/s and more depending on the physical network design
  • Up to 128 Base ID filters
  • Up to 64 Extended ID filters
  • 2 Configurable receive FIFO
  • Overload frame is generated on FIFO overflow
  • Up to 32 dedicated Transmit Buffers
  • Configurable Transit Buffers to FIFO or QUEUE
  • Configurable Transmit Event FIFO
  • Normal and Listen Only modes supported
  • Transmitter Delay Compensation up to six data bits long
  • Ability to abort transmission
  • Two configurable interrupt lines
  • Two clock domains (CAN clock and CPU clock)
  • Fully synthesizable
  • Static synchronous design with positive edge clocking and synchronous reset
  • Scan test ready
  • Available system interface wrappers:
  • AMBA – APB / AHB / AXI Lite Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus

Deliverables

  • HDL Source Code
  • Testbench environment
  • Automatic Simulation macros
  • Tests with reference responses
  • Synthesis scripts
  • Technical documentation
  • 12 months of technical support

Technical Specifications

Maturity
In Production
Availability
Immediately
Request Info

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