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DDR3 IP

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Compare 24 DDR3 IP from 12 vendors (1 - 10)
  • DDR3 and DDR4 Controller and PHY on TSMC 12nm
    • This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophisticated architecture and advanced technology.
    • Fabricated in TSMC’s 12nm CMOS process, this solution includes both controller and PHY IPs, providing comprehensive support for DDR3 and DDR4 memory interfaces.
    Block Diagram -- DDR3 and DDR4 Controller and PHY on TSMC 12nm
  • DDR3 SDRAM Controller
    • Supports industry standard Double Data Rate (DDR2 and DDR3) SDRAM.
    • Pipeline access allows continuous data bursting and hidden command execution.
    • Page hit detection supports fast column access and multiple open banks.
    • High speed implementation with standard DFI support for hard DDR PHY.
    Block Diagram -- DDR3 SDRAM Controller
  • DDR3 IP solution
    • Compatible with DDR3 up to 2133Mbps
    • AXI compliant multi-ports, and data width, FIFO depth, command queue depth configurable
    • DFI compliant interface between controller and PHY
    • Support ECC (error correcting code)
    Block Diagram -- DDR3 IP solution
  • GDDR3 Synthesizable Transactor
    • Supports 100% of GDDR3 protocol standard
    • Supports all the GDDR3 commands as per the specs
    • Supports all types of timing and protocol violation detection
    • Supports all mode registers programming
    Block Diagram -- GDDR3 Synthesizable Transactor
  • DDR PHY
    • DDR5/4/3 training with write-leveling and data-eye training
    • Optional clock gating available for low-power control
    • Internal and external datapath loop-back modes
    • I/O pads with impedance calibration logic and data retention capability
    • Programmable per-bit (PVT compensated) deskew on read and write datapaths
    • RX and TX equalization for heavily loaded systems
    Block Diagram -- DDR PHY
  • DDR multiPHY IP
    • Support for JEDEC standard DDR2, DDR3/3L/3U, LPDDR, and LPDDR2 SDRAMs
    • When combined with a Synopsys Universal DDR digital controller core and Verification IP Synopsys provides a complete multi-protocol DDR interface IP solution
    • Scalable architecture that supports from 0 to 1066 Mbps
    • DFI 2.1 interface to controller
    Block Diagram -- DDR multiPHY IP
  • Gen 2 DDR multiPHY IP
    • Support for JEDEC standard LPDDR2, LPDDR3, and DDR3 SDRAMs
    • Scalable architecture that supports data rates up to DDR3-2133
    • Support for DIMMs
    • Delivery of product as a hardened mixed-signal macrocell components allows precise control of timing critical delay and skew paths
    Block Diagram -- Gen 2 DDR multiPHY IP
  • DDR3/2 PHY - TSMC 40LP25
    • When combined with a Synopsys DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR3/2 interface IP solution
    • Scalable architecture that supports the speed range from DDR2-667 up to DDR3-2133
    • Support for DDR3L (1.35V DDR3)
    • Support for DDR2 and DDR3 DIMMs
    Block Diagram -- DDR3/2 PHY - TSMC 40LP25
  • DDR4/3 PHY - TSMC 16FFC
    • Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
    • High-performance DDR PHY supporting data rates up to 3200 Mbps
    • Compatible with JEDEC compliant DDR3/4 UDIMMs and RDIMMs as well as DDR4 LRDIMMs
    • Supports up to 16 logical ranks for high capacity memory requirements
    Block Diagram -- DDR4/3 PHY - TSMC 16FFC
  • DDR4/3 PHY - TSMC 16FF+GL
    • Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
    • High-performance DDR PHY supporting data rates up to 3200 Mbps
    • Compatible with JEDEC compliant DDR3/4 UDIMMs and RDIMMs as well as DDR4 LRDIMMs
    • Supports up to 16 logical ranks for high capacity memory requirements
    Block Diagram -- DDR4/3 PHY - TSMC 16FF+GL
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