DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process

Overview

It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage.

Technical Specifications

Short description
DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
Vendor
Vendor Name
Foundry, Node
UMC 130nm HS/FSG
UMC
Pre-Silicon: 130nm
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Semiconductor IP