PLL (Frequency Synthesizer) IP, Input: 133MHz - 266MHz, Output: Output: 133MHz - 266MHz, 266MHz - 533MHz, 533MHz - 1066MHz, UMC 0.13um HS/FSG process
Overview
Input 133MHz - 266MHz, output clock_1X 133MHz - 266MHz, output clock_2X 266MHz - 533MHz, output clock_4X 533MHz-1066MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process.
Technical Specifications
Foundry, Node
UMC 130nm HS/FSG
UMC
Pre-Silicon:
130nm
Related IPs
- DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
- PLL (Frequency Synthesizer) IP, Input: 12MHz, Output: 800MHz/1000MHz, 533MHz/666MHz, 400MHz/500MHz, 266MHz/533MHz, UMC 55nm SP process
- General Purpose Input / Output Controller (GPIO)
- 266MHz DLL (Vcc=1.8V,Fref=266MHz, Jitter=+/-100pS)
- 266MHz DLL (Vcc=1.8V, Freq=266MHz, Jitter=+/- 100pS)
- 32KHz input frequency Synthesizer PLL