DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
Overview
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process.
Technical Specifications
Foundry, Node
UMC 110nm HS/AE
UMC
Pre-Silicon:
110nm
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