DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
Overview
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic process.
Technical Specifications
Short description
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
Vendor
Vendor Name
Foundry, Node
UMC 110nm HS/FSG
UMC
Pre-Silicon:
110nm
Related IPs
- DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
- UMC L90SP 90nm DDR DLL - 80MHz-400MHz
- UMC L90SP 90nm DDR DLL - 60MHz-300MHz
- DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
- DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
- DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process