AES + SHA DMA Crypto Accelerator

Overview

The EIP-120 is a low-power low-gatecount crypto core with DMA capability and local key storage. Compared to a software only solution, the core provides higher performances and additional security to applications.
By using dedicated hardware accelerators, the EIP-120 provides a first performance boost compared to software execution on the host processor. The second advantage is the ability to store keys in an integrated RAM via DMA, and keep these inaccessible, but usable, for the host/application.

Key Features

Control interface
- Simple register based control interface
- Operation done interrupt
- DMA done interrupt
Crypto Algorithms (AES)
- 128, 192 and 256-bit key support
- AES-ECB/CBC/CTR
- AES-CBC-MAC
- AES-CCM
- AES-GCM (Optional, by default available)
- Internal GCM hash key calculation
- Key load via the Key Store only
- IV writing and reading via slave interface
- Data load via the slave and DMA
- Data readout via the slave and DMA
- Tag readout via the slave and DMA
Hash Algorithms
- SHA-256 / SHA-224
- SHA-512 / SHA-384
- Basic hash
- HMAC (using several basic hash operations)
DMA Controller
- Two channels (inbound, outbound)
- 16-bit DMA length
AHB Interface (AMBA V2.0)
- 32-bit AHB slave interface for configuration and data
- 32-bit AHB master interface for keys, crypto and hash blocks
- Optional use of privileged accesses for key reads
AXI Interface (AMBA V3.0)
- 32-bit and 64-bit AXI master and slave interface available on request
Embedded Memory
- Key store RAM: 32x32 bit 1 port RAM
Symmetric crypto performance
- Raw engine performance at 500 MHz
  - 1230 Mbps AES (128-bit key)
  - 1030 Mbps AES (192-bit key)
  - 888 Mbps AES (256-bit key)
- Hash block performance
  - Raw engine performance at 500 MHz
    - 3938 Mbps SHA-256 Digest and length load via the slave
  - Data load via the slave and DMA
  - Digest readout via the slave and DMA
- Key Store
  - Secure management of sensitive security parameters
  - Local 8 x 128-bit (or 4 x 192-bit/256-bit) encryption key storage
  - Writable via DMA only
- DMA Controller
  - Two channels (inbound, outbound)
  - 16-bit DMA length
- AHB Interface (AMBA V2.0)
  - 32-bit AHB slave interface for configuration and data
  - 32-bit AHB master interface for keys, crypto and hash blocks
  - Optional use of privileged accesses for key reads
- AXI Interface (AMBA V3.0)
  - 32-bit AXI master and slave interface
  - 64-bit AXI master and slave interface available on request
- Embedded Memory
  - Key store RAM: 32x32 bit 1 port RAM

Benefits

Low-power Crypto core
Silicon-proven implementation
Fast and easy to integrate into SoCs
Flexible layered design
Complete range of configurations
World-class technical support

Applications

IoT Security

Deliverables

Documentation
- Hardware Reference and Programmer Manual
- Integration Manual
- Verification Specification
Synthesizable Verilog RTL source code
Self-checking RTL test bench, including test vectors and expected result vectors
Simulation scripts
Synthesis scripts
Configurations:
Many different configurations available:
- Local key Store
- Gate counts range from : 49-79k gates, depending on CMOS nodes
- AES with all key sizes and modes
- AES-128: 947 Mbps at max freq
- AES-128: 1286 Mbps at max freq
- AES-128: 1480 Mbps at max freq
- SHA-256 / SHA-224 / SHA-512 / SHA-384 / HMAC
- SHA-256: 3553 Mbps at max freq
- SHA-512: 5700 Mbps at max freq
- SHA-256: 4759 Mbps at max freq
- SHA-512: 7634 Mbps at max freq
- SHA-256: 5980 Mbps at max freq
- SHA-512: 9593 Mbps at max freq
- For more information about this product or the all the different configurations, please contact Rambus: https://www.rambus.com/contact

Technical Specifications

Foundry, Node

Any

Maturity

Silicon Proven

Availability

Now

TSMC

Silicon Proven: 7nm , 16nm , 28nm , 40nm G

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