32-bit PCI Bus Master/Target

Overview

Key Features

• 32-bit PCI interface
• AMBA AHB 2.0 back end interface
• Parametrizable FIFOs for both master and target operation
• Combined bus master and target
• Supports incremental bursts and single accesses
• Bus master capabilities:
• Memory read, memory write
• Memory read multiple
• Memory read line
• Memory write and invalidate
• I/O Read, I/O Write
• Type 0 configuration Read, configuration Write
• Bus Parking
• Host Bridging
• Target capabilities:
• Type 0 Configuration Space Header
• Configuration Read, Configuration Write
• Parity Generation (PAR), Parity Error Detection (PERR# and SERR#)
• 2 Memory BARs
• Memory read, memory write
• Memory read multiple
• Memory read line
• Memory write and invalidate
• Optional DMA engine add on

Benefits

• Available in GPL for evaluation
• Low cost commercial license
• Easily integrated through AMBA plug&play
• Low-area overhead

Deliverables

• Fully synthesisable VHDL code
• VHDL test bench
• Ducumentation
• Optional FPGA evaluation board

Technical Specifications