The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems. It includes parameterizable FIFOs for both master and target operation, and can optionally be provided with an independent DMA engine.
PCI Bridge
Overview
Key Features
- 2-bit PCI interface
- PCI bus master and target
- AMBA AHB/APB 2.0 back-end interface
- Configurable FIFOs for both master and target operation
- Supports incremental bursts and single accesses
- Bus master capabilities
- Memory read, memory write
- Memory read multiple
- Memory read line
- I/O read, I/O write
- Type 0 and 1 configuration read and write
- Host bridging
- Target capabilities
- Type 0 configuration space header
- Configuration read and write
- Parity generation (PAR)
- 2 Memory BARs
- Memory read, memory write
- Memory read multiple
- Memory read line
- Memory write and invalidate
- Optional DMA engine add on
- Software support for GRPCI hosts in Linux 2.6, RTEMS and VxWorks
Benefits
- Available in GPL for evaluation
- Low cost commercial license
- Easily integrated through AMBA plug&play
- Low-area overhead
Deliverables
- Fully synthesisable VHDL code
- VHDL test bench
- Ducumentation
- Optional FPGA evaluation board
Technical Specifications
Short description
PCI Bridge
Vendor
Vendor Name
Foundry, Node
Any
Maturity
Production
Availability
Immediate