The CMOS high-frequency divider consists of two independent circuits. The first divider is a set of serially connected CMOS dividers with a dividing ratio 2. The second circuit is based on ECL logic and has differential signal. The reference current source of ECL circuit has temperature dependent and temperature independent modes. The buffer-commutators are used to output the signal of a frequency divided by 2, 64 or 128.
The block is fabricated on TCMS BiCMOS 0.18 um technology.
2/64/128 CMOS/ECL PLL high-frequency divider
Overview
Key Features
- TSMC BiCMOS SiGe 180 nm
- Fixed dividing ratio 128 with complementary outputs of dividers on 2 and 64
- Two divider types: CMOS and ECL
- Temperature dependent mode of reference current
- Portable to other technologies (upon request)
Block Diagram
Applications
- PLL frequency synthesizer
Deliverables
- Schematic or NetList
- Layout or blackbox
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC BiCMOS SiGe 180 nm
Maturity
Silicon proven
Availability
Now
TSMC
Silicon Proven:
180nm