The CMOS PLL high-frequency divider consists of the converter of a differential input signal to an unipolar signal with a supply voltage peak-to-peak, a prescaler with variable dividing ratio 4/5 and two binary decade counters.
The block is fabricated on TCMS BiCMOS 0.18 um technology.
Programmable CMOS PLL high-frequency divider
Overview
Key Features
- TCMS BiCMOS 0.18 um
- Wide range of dividing ratio 16…1023
- Low current consumption
- Compact structure
- Portable to other technologies (upon request)
Applications
- PLL frequency synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC BiCMOS SiGe 180 nm
Maturity
Silicon proven
Availability
Now
TSMC
Silicon Proven:
180nm
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