Video and image processing design using FPGAs
By Brian J. Jent, Altera Corp.
Courtesy of Video/Imaging DesignLine (07/07/2006 0:40 AM EDT)
New trends in video and image processing are forcing developers to re-examine the design architectures they have used previously when considering the numerous tradeoffs of using different architectures that are key to the decision process.
Consumer demand and exciting innovations, such as HDTV and digital cinema, revolve around video and image processing and the rapid evolution of the technology. Major advancements in image capture and display resolutions, advanced compression techniques, and video intelligence are the driving forces behind these technological innovations. At the same time, rapid change in standards and higher resolutions are pushing designers away from off-the-shelf technology.
Resolutions in particular have increased dramatically in just the last few years. The following table illustrates current state-of-the-art resolutions in different end types of applications.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- Video and image processing design using FPGAs
- Using vector processing for HD video scaling, de-interlacing, and image customization
- Implementing digital processing for automotive radar using SoC FPGAs
- Designing low-power video image stabilization IP for FPGAs
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design