Realising the Full Potential of Multi-core Designs
Multi-core chips offer performance, scalability, low-power and flexibility, but are they useable by software engineers? New start-up, Ignios, is addressing these issues.
ASIC, ASSP, FPGA and other System on Chip (SoC) designs containing multiple processor cores are becoming the preferred hardware platforms for many applications. Compared with uni-processor architectures, multi-core chips have the potential to provide a far higher level of price-performance. These chips combine specialist engines within a single design, which may include any configuration of multiple CPUs, DSPs and co-processors. With multi-core, a new class of flexible software-programmable designs are permeating the SoC and merchant semiconductor market. According to analysts, the multi-processor SoC segment is forecast to grow at a compound annual rate of around 30 percent.
Recent multi-core commercial designs target applications such as network processors, recordable DVDs, set-top boxes, HDTV platforms, mobile handsets and many others. The number of cores within a single design ranges from a couple to over 150. The most prevalent example of a multi-core application is the ubiquitous mobile handset; many GSM devices contain a single digital chip comprising a DSP for baseband processing and a general-purpose processor for handling the application requirements.
Click here to read more ...
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related Articles
- Realising the Full Potential of Multi-core Designs
- The Benefits of a Multi-Protocol PMA
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Reusable debug infrastructure in multi core SoC : Embedded WiFi case study
Latest Articles
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension
- ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes
- In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
- David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
- RoMe: Row Granularity Access Memory System for Large Language Models