Pragmatic Adoption of Formal Analysis
Anders Nordstrom, Cadence Design Systems, Inc.
(03/29/2007 9:10 AM EDT), EE Times
Introduction
Verification of today's system-on-chip (SoC) designs is a hard problem that keeps getting harder. Design size and complexity continually increase, while the market demands ever-tighter development schedules. Multiple approaches such as directed and coverage-driven random simulations, assertion-based verification, and formal analysis are needed to most effectively verify a chip. This article focuses specifically on the technique of formal analysis and discusses how to adopt it efficiently on SoC projects.
(03/29/2007 9:10 AM EDT), EE Times
Introduction
Verification of today's system-on-chip (SoC) designs is a hard problem that keeps getting harder. Design size and complexity continually increase, while the market demands ever-tighter development schedules. Multiple approaches such as directed and coverage-driven random simulations, assertion-based verification, and formal analysis are needed to most effectively verify a chip. This article focuses specifically on the technique of formal analysis and discusses how to adopt it efficiently on SoC projects.
To read the full article, click here
Related Semiconductor IP
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
Related Articles
- Getting the most out of formal analysis
- Formal Verification IPs: the corner stone for a broader adoption of Formal Verification
- Case Study: Can you afford to ignore formal analysis?
- Using verification coverage with formal analysis
Latest Articles
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation