Practical Power Network Synthesis For Power-Gating Designs
Kaijian Shi, Zhian Lin, Yi-Min Jiang, Synopsys, Inc.
(06/05/2007 3:00 AM EDT), EE Times
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.
This method simultaneously optimizes the number and positions of sleep transistors and the power network's grids and wires for minimum area, maximum routeability with a given IR-drop target. With this automated method for synthesizing the power network, you can more easily take advantage of power gating to reduce leakage power consumption dramatically in SoCs.
(06/05/2007 3:00 AM EDT), EE Times
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.
This method simultaneously optimizes the number and positions of sleep transistors and the power network's grids and wires for minimum area, maximum routeability with a given IR-drop target. With this automated method for synthesizing the power network, you can more easily take advantage of power gating to reduce leakage power consumption dramatically in SoCs.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related Articles
- Context Based Clock Gating Technique For Low Power Designs of IoT Applications - A DesignWare IP Case Study
- Akida Exploits Sparsity For Low Power in Neural Networks
- A modeling approach for power integrity simulation in 3D-IC designs
- Memory solution addressing power and security problems in embedded designs
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks