Multicore SoCs change interconnect requirements
Greg Shippen, Freescale Semiconductor
EE Times (10/20/2008 12:01 AM EDT)
The recent appearance of multicore system-on-chip (SoC) devices has rearranged the boundaries among silicon devices, boards and subsystems. This trend has led to significant changes in chip-to-chip and board-to-board interconnect requirements. Are existing standards-based interconnects ready for this transition?
With the introduction of the microprocessor in the 1970s, simple computing systems were constructed on a single board using a discrete processor, memory controller and I/O interface device. Board-level buses connected the devices; when higher performance was desired, multiple boards were assembled together. Backplanes provided communication between cards using a system-level bus.
These board- and system-interconnect protocols were proprietary. Over time, closed protocols gave way to standardized protocols such as Ethernet, PCI Express or RapidIO.
EE Times (10/20/2008 12:01 AM EDT)
The recent appearance of multicore system-on-chip (SoC) devices has rearranged the boundaries among silicon devices, boards and subsystems. This trend has led to significant changes in chip-to-chip and board-to-board interconnect requirements. Are existing standards-based interconnects ready for this transition?
With the introduction of the microprocessor in the 1970s, simple computing systems were constructed on a single board using a discrete processor, memory controller and I/O interface device. Board-level buses connected the devices; when higher performance was desired, multiple boards were assembled together. Backplanes provided communication between cards using a system-level bus.
These board- and system-interconnect protocols were proprietary. Over time, closed protocols gave way to standardized protocols such as Ethernet, PCI Express or RapidIO.
To read the full article, click here
Related Semiconductor IP
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
Related Articles
- Using dynamic run-time scheduling to improve the price-performance-power efficiency of heterogeneous multicore SoCs
- Multicore microprocessors and embedded multicore SOCs have very different needs
- Build low power video SoCs with programmable multi-core video processor IP
- Using drowsy cores to lower power in multicore SoCs
Latest Articles
- GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
- Creating a Frequency Plan for a System using a PLL
- RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
- MING: An Automated CNN-to-Edge MLIR HLS framework
- Fault Tolerant Design of IGZO-based Binary Search ADCs