Moving to SystemC TLM for design and verification of digital hardware
Stuart Swan, Qiang Zhu, Xingri Li, Cadence Design Systems, Inc.
EETimes (5/13/2013 9:35 AM EDT)
Design and verification of new digital hardware blocks is becoming increasingly challenging. Today, designers are confronted with a host of issues, including growing design and verification complexity, time-to-market pressures, power goals, and evolving design specifications.
To tackle these challenges, customers are beginning to make a significant change in design methodology, by moving to SystemC transaction-level models (TLM) as the design entry point, and by leveraging high-level synthesis (HLS) in combination with IP reuse. This article presents our experience in working with Fujitsu Semiconductor Ltd. to adopt this new methodology using Cadence® C-to-Silicon Compiler on a data access controller design, and presents the very promising results they reported at a recent C-to-Silicon user group meeting in Japan. The selection of the design, modeling work, and results analysis described in this paper were performed by Fujitsu Semiconductor with some assistance from Cadence.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Articles
- Automotive Design Needs Efficient Verification to Survive
- Importance of VLSI Design Verification and its Methodologies
- Design-Stage Analysis, Verification, and Optimization for Every Designer
- Shift Left for More Efficient Block Design and Chip Integration
Latest Articles
- FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
- MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
- AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing
- FeNN-DMA: A RISC-V SoC for SNN acceleration
- Multimodal Chip Physical Design Engineer Assistant