Moving to SystemC TLM for design and verification of digital hardware
Stuart Swan, Qiang Zhu, Xingri Li, Cadence Design Systems, Inc.
EETimes (5/13/2013 9:35 AM EDT)
Design and verification of new digital hardware blocks is becoming increasingly challenging. Today, designers are confronted with a host of issues, including growing design and verification complexity, time-to-market pressures, power goals, and evolving design specifications.
To tackle these challenges, customers are beginning to make a significant change in design methodology, by moving to SystemC transaction-level models (TLM) as the design entry point, and by leveraging high-level synthesis (HLS) in combination with IP reuse. This article presents our experience in working with Fujitsu Semiconductor Ltd. to adopt this new methodology using Cadence® C-to-Silicon Compiler on a data access controller design, and presents the very promising results they reported at a recent C-to-Silicon user group meeting in Japan. The selection of the design, modeling work, and results analysis described in this paper were performed by Fujitsu Semiconductor with some assistance from Cadence.
To read the full article, click here
Related Semiconductor IP
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
Related White Papers
- Automotive Design Needs Efficient Verification to Survive
- Importance of VLSI Design Verification and its Methodologies
- Design-Stage Analysis, Verification, and Optimization for Every Designer
- Shift Left for More Efficient Block Design and Chip Integration
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS