Single Flow for Interconnecting IP
June 20, 2008 -- edadesignline.com
The latest challenge facing SoC teams is the construction of a design flow that seamlessly combines:
- A complex central Interconnect Matrix
- Auto generation of a diverse range of system design views
In this article, we outline a flow, based around industry proven and emerging 'capture and auto generation' EDA solutions, which results in seamless interoperability between disparate tools and methods.
While, suppliers of Interconnect Matrix components provide complex architectures for hardware, the SoC team is also responsible for producing other associated design view outputs such as documentation and code for software development, test and verification. Ultimately the team is responsible for delivering a fully tested, documented and usable product " on time.
A central Interconnect Matrix allows a designer to create multiple memory maps and control communications paths based on specific master and slave combinations easily and quickly. The design and creation of an Interconnect Matrix component is well defined and tools providing suitable architectures are available, from companies such as Sonics, ARM, Arteris etc.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- Plug-n-play UVM Environment for Verification of Interrupts in an IP
- IP Exchange Through Handoff for Easy System-On-Chip Design
- Design Rights Management of Intellectual Property (IP) Cores in SoPC designs
- Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP
Latest White Papers
- SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems