Improving the Testability of Complex SoC Designs
It is well known that testing System-on-Chip (SoC) designs poses technological and economic challenges. With complex SoCs targeted at cost-sensitive consumer applications, especially in the communications arena, it is important to minimize testing costs as much as possible. For this reason, Design-for-Test (DFT) is critical to the success of these chips. In fact, unique and significant test cost reductions can be achieved if DFT can be extended to exploit highly flexible tester resources.
Recent extensions in DFT techniques enable the Concurrent Test (CCT) of circuit blocks within an SoC by isolating target IP cores and ensuring that chip resources are allocated such that the cores can be tested in parallel. To effectively utilize this type of concurrent test, designers should be aware of the procedures, enhanced design automation and test system capabilities needed to implement highly tuned concurrent test.
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related White Papers
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- Out of the Verification Crisis: Improving RTL Quality
- Getting started in structured assembly in complex SoC designs
- Streamlining SoC Integration With the Power of Automation
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY