Getting started in structured assembly in complex SoC designs
By Tim Schneider, Arteris IP (July 27, 2022) - EDN
The integration level of a system-on-chip (SoC) is defined in RTL, just like the rest of the design. Historically, RTL has been built through text editors. However, a decade or more ago, the sheer complexity of that task for the largest SoCs became unmanageable; now, most SoCs cross that threshold. Why is this? The number of IPs in the SoC is certainly a factor, and the number of connections explodes at the integration level. For example, a single AXI channel connection can have 25 signals. Next, AMBA to AMBA connections in multiple flavors proliferate across designs.
Also, designers must include the integration infrastructure—clocks, resets, power management and test—which must evolve as the design progresses. These requirements can add up to 10,000 connections in an unexceptional SoC. Connections between IPs may have hundreds of ports with multiple configuration tie-off options. These ports may be left open or connected and have many other significant considerations. Typical interconnect complexity is evident even in a small subset of the design.
To read the full article, click here
Related Semiconductor IP
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
Related White Papers
- Analog and Power Management Trends in ASIC and SoC Designs
- Optimizing Communication and Data Sharing in Multi-Core SoC Designs
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- Understanding LTTPR: Enabling High-Speed DisplayPort Interconnects in Complex System Designs
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS