Implementing PCI Express Designs using FPGAs

Today's 90 nm FPGAs offer high performance and cost effective platforms to implement single-chip and two-chip PCI Express solutions, making them the ideal platforms for PCI Express.

By Abhijit Athavale, Xilinx

As the industry transitions from shared, arbitrated, bus-based system interconnect architectures like PCI to high-performance, serial, point-to-point architectures like PCI Express, designers are looking for implementations that allow them to save costs without affecting performance. They must choose from several alternatives – such as FPGAs and several flavors of ASICs and ASSPs – based on system requirements such as performance, volume, cost, etc. While each approach has its merits, FPGAs offer a total cost of ownership advantage as compared to ASICs or ASSPs for most embedded applications. With a short time-to-market and no up-front NRE, programmable logic eliminates the excessive costs related to the supply chain such as inventory and costs related to multiple suppliers and multiple product qualification cycles. Plus, the risk reduction benefits associated with FPGAs, their continuously improving performance, and their ability to offer instant gratification to the designer cannot be overlooked.

Cell-based ASICs/ASSPs are still the way to go when performance or functionality requirements are extreme and volume requirements are in the millions per year. When implementing a root complex, for example, chances are that an ASSP solution is already available. Of course, if the plan is to build a custom root complex that implements a superset or subset of the specification, then an FPGA would be ideal. When building a switch with multiple ports and very high bandwidth requirements, an existing ASSP or ASIC implementation may be available.. If the implementation will be a PCI Express endpoint – like most embedded applications – FPGAs will most-likely be the ideal choice.

Today's high-end 90nm FPGAs such as the Virtex-4 family offer performance that matches those of ASICs/ASSPs for x1, x4 or x8 lane PCI Express endpoint implementations, while the Spartan-3 generation FPGAs offer very low cost x1 PCI Express implementations for mid-high volume markets. Before selecting a technology for implementing a PCI Express design, designers must carefully look at several factors such as logic performance, gate count, link efficiency, compliance testing, and ease of implementation. This article will review the considerations for building PCI Express design in the latest 90nm FPGAs.

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