Getting the most out of ASIC prototyping with FPGAs

Over the past 18 months, there has been a growing adoption of the use of FPGAs to prototype ASICs as part of an ASIC verification methodology. With the development costs for ASICs skyrocketing – a typical 90nm ASIC/SoC design tape-out today costs around $20M; a 90nm mask set alone costs over $1M; and total development cost for a 45nm SoC is expected to top $40M – it is clear to see why avoiding a respin by prototyping with FPGAs is attractive.

Besides the increase in mask set cost, total development cost is also increasing due to the reduced probability of getting the design right the first time. As design complexity continues to increase, surveys have shown that only about a third of today's SoC designs are bug-free in first silicon, and nearly half of all re-spins are reported as being caused by functional logic error. As a result, verification managers are now exploring ways to strengthen their functional verification methodologies.

With increased complexity, another cost becomes a limiting factor to the effectiveness of verification – simulation runtime and inaccuracy of stimulus models. Prototyping an ASIC design in FPGAs, while often yielding different performance, still results in the same logical functionality. Further, running a design at speed on an FPGA prototype with real stimulus allows for a far more exhaustive and realistic functional coverage as well as early integration with embedded software. Thus FPGA prototyping can be used effectively to supplement and extend existing functional verification methodologies.

When adopting an FPGA prototyping flow, there are a number of important issues a designer has to consider as follows:

• Partitioning the design across multiple FPGAs
• Translating ASIC primitives to FPGA logic cells
• Conversion of gated clocks
• Support for DesignWare libraries
• Coding for memory portability
• Support for ASIC constraint files

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