Tips and Tricks: Using FPGAs in reliable automotive system design
automotivedesignline.com (January 15, 2009)
For FPGAs to be part of an ultra-reliable design, designers must protect the valid FPGA configuration used for initialization and prevent SRAM corruption during device operation
The increased use of complex automotive electronics systems requires that they be designed for "ultra-reliability," because the failure of an automotive system could place the vehicle's passengers in a life-threatening situation. System designers are considering the use of Field Programmable Gate Arrays (FPGAs) more frequently in these systems, due to the FPGA's ability to integrate and perform complex functions.
However, there are two primary concerns regarding the use of FPGAs in automotive systems: The need to protect the valid FPGA configuration used for initialization, and prevention of SRAM corruption during device operation. Unless these concerns are fully addressed, FPGAs cannot be part of an ultra-reliable automotive system design.
Fortunately, current AEC-Q100 qualified FPGAs incorporate several advanced features that resolve these concerns. This article will highlight several solutions that address both the initialization configuration and potential SRAM corruption issues.
To read the full article, click here
Related Semiconductor IP
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
Related White Papers
- Designing FPGA Based Reliable Systems Using Virtex-5 System Monitor
- Get More Reliable Automotive ICs with a Shift Left Design Approach
- FPGA based Complex System Designs: Methodology and Techniques
- A 24 Processors System on Chip FPGA Design with Network on Chip
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS