FPGA Design: Faster Runtimes & Increased Productivity
Joe Mallet, Synopsys
EETimes (1/13/2016 04:40 PM EST)
In order to achieve accelerated FPGA development schedules, designers require the aid of sophisticated synthesis tools.
FPGA device density is continuing to grow at approximately 2x per node, which is -- not surprisingly -- driving larger, more complex designs. This means that FPGA designers face several challenges as follows:
- Longer run times due to increasing design size and complexity.
- Achieving rapid synthesis turn-around time to integrate design changes.
- Avoiding unnecessary resynthesizing of pre-verified, static modules, like IP blocks and completed modules.
In order to achieve accelerated FPGA development schedules, while supporting increasing design sizes and complexity, designers require the aid of sophisticated synthesis tools.
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- Increased Verification Productivity through extensive Reuse
- A tutorial on tools, techniques, and methodology to improve FPGA designer productivity
- Medical imaging process accelerated in FPGA 82X faster than software
- Achieving Better Productivity with Faster Synthesis
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks