FPGA Design: Faster Runtimes & Increased Productivity
Joe Mallet, Synopsys
EETimes (1/13/2016 04:40 PM EST)
In order to achieve accelerated FPGA development schedules, designers require the aid of sophisticated synthesis tools.
FPGA device density is continuing to grow at approximately 2x per node, which is -- not surprisingly -- driving larger, more complex designs. This means that FPGA designers face several challenges as follows:
- Longer run times due to increasing design size and complexity.
- Achieving rapid synthesis turn-around time to integrate design changes.
- Avoiding unnecessary resynthesizing of pre-verified, static modules, like IP blocks and completed modules.
In order to achieve accelerated FPGA development schedules, while supporting increasing design sizes and complexity, designers require the aid of sophisticated synthesis tools.
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related Articles
- Increased Verification Productivity through extensive Reuse
- A tutorial on tools, techniques, and methodology to improve FPGA designer productivity
- Medical imaging process accelerated in FPGA 82X faster than software
- Achieving Better Productivity with Faster Synthesis
Latest Articles
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
- A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
- FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design