Facilitating at-speed test at RTL (Part 2)
Dr. Ralph Marlett, Kiran Vittal, Atrenta Inc.
4/20/2011 2:15 AM EDT
Part 1 of this series discusses the problems with at-speed testing, and the various defect models and manufacturing test techniques. This part will tackle at-speed timing closure rules and at-speed coverage. It also looks into the at-speed coverage estimation and diagnosis of SpyGlass-DFT DSM.
The SpyGlass-DFT DSM product provides timing closure analysis and RTL testability for deep subµm (DSM) defects associated with at-speed testing. It is touted to provide accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low fault coverage, early in the design flow.
Figure 1: Complete RTL analysis solution for stuck-at and at-speed testing.
To access the full Design Article by Atrenta Inc. (in PDF Format), click here.
Read also:
Facilitating at-speed test at RTL (Part 1)
About the authors:
. Dr. Ralph Marlett, Product Director, Atrenta Inc.
. Kiran Vittal, Product Marketing Director, Atrenta Inc.
Courtesy of EE Times India
Related Semiconductor IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- LLM AI IP Core
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
Related White Papers
- Facilitating at-speed test at RTL (Part 1)
- Moving DFT to RTL overcomes test vector issues
- Static Checks for Power Management at RTL
- Power analysis of clock gating at RTL
Latest White Papers
- SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems