Overcoming the challenges of formal verification and debug

Vennsa Technologies Inc.
ETTimes (5/18/2011 9:08 AM EDT)

It is well known that verification is a major time and effort drain in today’s design process. For some time now, advocates of formal verification and property checking have promoted this technology as the timely solution to the ballooning verification pain. Indeed, the arguments are compelling: there is no need to develop a standalone testbench or to generate stimulus to cover corner cases, and once a property passes it is 100 percent correct. All one needs to achieve these benefits is to write a set of properties and run a property checker to prove or disprove the compliance of these properties by the design. For these reasons in the early to mid 2000s EDA companies large and small dedicated much effort and money to develop and capture a segment of this new market.

Over the years that followed, as many companies and engineers learned through firsthand experience, there are some major obstacles to overcome to make the formal verification argument a reality in practice. In my view, there are two main challenges (1) writing assertions is complicated, (2) debugging property failures can be significantly more difficult than that of a human developed testbenches.

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