Tiles - An Architectural Abstraction for Platform-Based Design
by Drew Wingard
The relentless pace of Moore's Law has caught up with us again. Design teams still struggling under the weight of system-on-a-chip (SOC) designs composed of hopefully-reusable-next-time IP cores are running head-first into a new challenge-trying to manage the interactions of 50 or more somewhat independent cores throughout the design process. What is needed is a new level of abstraction-a level of hierarchy that reduces the number of objects to something a designer can effectively reason over. Some people call this next level of abstraction the platform, but most platform definitions imply a single "metacore" integrating a critical subset of the desired functions that is then integrated with a set of application-specific peripherals.
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related White Papers
- An FPGA-to-ASIC case study for refining smart meter design
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- The role of sockets in platform based design: a case study of the OMAP platform
- System CoreWare Based Design using RapidChip Platform ASIC
Latest White Papers
- Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard