Tiles - An Architectural Abstraction for Platform-Based Design
by Drew Wingard
The relentless pace of Moore's Law has caught up with us again. Design teams still struggling under the weight of system-on-a-chip (SOC) designs composed of hopefully-reusable-next-time IP cores are running head-first into a new challenge-trying to manage the interactions of 50 or more somewhat independent cores throughout the design process. What is needed is a new level of abstraction-a level of hierarchy that reduces the number of objects to something a designer can effectively reason over. Some people call this next level of abstraction the platform, but most platform definitions imply a single "metacore" integrating a critical subset of the desired functions that is then integrated with a set of application-specific peripherals.
Related Semiconductor IP
- MIPI D-PHY RX+ (Receiver) IP
- MIPI D-PHY TX+ (Transmitter)
- LVDS Deserializer IP
- LVDS Serializer IP
- MIPI D-PHY/LVDS Combo Receiver IP
Related White Papers
- An FPGA-to-ASIC case study for refining smart meter design
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- Infinite-ISP: An Open Source Hardware Image Signal Processor Platform for all Imaging Needs
- The role of sockets in platform based design: a case study of the OMAP platform
Latest White Papers
- DisplayPort 2025: Navigating the Next Wave of Display Innovation
- Efficient Magnetization Switching via Orbital-to-Spin Conversion in Cr/W-Based Heterostructures
- Real-Time ESD Monitoring and Control in Semiconductor Manufacturing Environments With Silicon Chip of ESD Event Detection
- Benchmarking Ultra-Low-Power 𝜇NPUs
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency