Tackling large-scale SoC and FPGA prototyping debug challenges
Brad Quinton, Tektronix
EETimes (1/21/2013 11:06 AM EST)
When designing complex ASICs, such as a highly-integrated system-on-chip (SoC), engineers are highly motivated to perform comprehensive verification under as real-world operating conditions as possible to ensure that bugs can be identified and corrected before final tapeout. The source of the motivation, of course, is the high-cost and time required to re-spin an ASIC.
While discovering and tracking down the root cause of bugs can be challenging in the best of circumstances, inherent limitations in the various technologies available to ASIC designers for verification testing make the job much harder as each involves a variety of tradeoffs. Now, however, new technologies are emerging that offer the promise of much more efficient and less time intensive debug processes using FPGA prototypes.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related White Papers
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- FPGA Prototyping of Complex SoCs: RTL code migration and debug strategies
- Virtual prototyping boosts model-driven Design for Six Sigma methodology: Part 1 of 3 - The challenges and tools