Standard Debug Interface Socket Requirements For OCP-Compliant SoC

Abstract

Debug for SoC adds new requirements and challenges in terms of adding visibility and control to a system, simplifying integration of hardware and software instrumentation into design flows, and supporting emerging needs for architectures incorporating complex network on chip buses, multiple cores, multithreading, embedded security, power management and other issues. The OCP-IP Debug Working Group addresses the definition of debug resources and integration to enable comprehensive debug of OCP based systems. Contributors include OCP-IP companies (IP venders, systems integrators, end customers) addressing the need for debug solutions and/or debug of the OCP Infrastructure.

The initial focus is on definition of debug signals at the OCP Socket and fabric levels, but leaves their specific implementation open to IP and tools venders. The scope does not address in detail the external debug interfaces between an OCP Debug Interface Socket with on-chip Debug environment and external components (probes, debuggers, etc). These pin level interfaces are considered separate from the OCP Debug System and are being addressed by other industry working groups (Nexus, MIPI, IJTAG, Multicore Association Debug Working Group, etc). The OCP Debug Infrastructure defines requirements for interfaces between the Debug and EDA infrastructure and features, but does not address specific debug to EDA interfaces, which are again specific to different implementations.

1. Introduction

Debugging and Monitoring of SoC are important capabilities to supporting better quality and time to market hardware and software solutions. Debug is an emerging area in SoC design, with many facets to consider. The OCP-IP Debug Working Group is focused to standardizing a set of OCP debug interfaces to enable new and more rapid application of system debug/observation/cross-triggering IP and software solutions.

In recent years, the Open Core Protocol (OCP) paradigm has become an accepted solution for delivering high-performance on-chip interconnect fabrics for massive multi-core systems-on-chip. A special class of this paradigm is the multi-processor systems-on-chip (MP-SoCs). This document outlines a matching concept of system wide debug of heterogeneous MP-SoC using a standardized OCP bus interface for all IP blocks.

The essence of the proposed debug solution is an optional OCP port, known as the Debug Interface Socket, which may be added to all cores and IP blocks that support or need debugging access. The Debug Interface Socket is an OCP port with a restrictive configuration that is limited specifically to support debug interactions. The Debug Interface Socket may communicate off chip via a number of mechanisms; most common being a test port or memory mapped interface to processor. If debug blocks are memory mapped, then the normal OCP Data Socket is added to the debug socket to interface to on-chip IP blocks and cores. The Socket IP is ideally supported by a commercial infrastructure of tools, SystemC and other transaction based ESL and virtual debug block models, which complement the emerging trends in SoC design flows, and which interact with other OCP IP to provide comprehensive IP based debug solutions.

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