SoC RTL Signoff: Divide & Conquer with Abstract Models
Anuj Kumar and Kiran Vittal, Atrenta
EETimes (6/1/2015 00:00 AM EDT)
One of the fastest, easiest, and most effective methods to detect and remove bugs early in the design phase, is to run lint checks on the RTL. Besides coding guidelines, these tools catch issues related to simulation, synthesis, and place & route. A robust lint methodology reduces long and costly iterations between RTL design and downstream verification and implementation.
Typical System-on-Chip (SoC) designs have become far bigger (>100M gates) and more complex than they were just a few years ago. This has added serious challenges and roadblocks to the successful completion of the full, chip-level analysis within the desired project cycle for RTL signoff. One of the fastest, easiest, and most effective methods to detect and remove bugs early in the design phase, is to run lint checks on the RTL. Besides coding guidelines, these tools catch issues related to simulation, synthesis, and place & route. A robust lint methodology reduces long and costly iterations between RTL design and downstream verification and implementation.
Some of the common challenges of this early analysis, include the tool’s capacity and performance, management of the voluminous rule violations at the SoC level, and ensuring the portability of block level waiver constraints for chip level analysis. Due to limited availability of time and resources, these challenges often lead to incomplete RTL analysis, while negatively impacting the overall quality of results (QoR) and adding significant delay to project schedules.
This article will highlight many of the issues faced by designers working on the next generation SoC designs. These designers face many challenges while doing the chip-level lint analysis using a traditional ‘flat’ design approach. We will look at ways to boost the designer’s productivity, while coming up with an efficient, robust, and scalable chip-level, hierarchical analysis flow.
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