Dealing with SoC metastability problems due to Reset Domain Crossing
Arjun Pal Chowdhury , Neha Agarwal and Ankush Sethi, Freescale Semiconductor India Pvt LTD
embedded.com (November 10, 2013)
Metastability in design due to asynchronous clock domain crossing (CDC) is a well known problem. Industry standard advanced tools are available to catch such structural or functional issues in design.
However, CDC is not the only reason a signal becomes asynchronous with respect to the destination clock domain. In a sequential design, if the reset of source register is different from the reset of destination register even though the data path is in same clock domain, this will create an asynchronous crossing path and cause metastability at destination register. Referred to as Reset Domain Crossing (RDC), it occurs when the reset signals of launch and capture flops are different.
This article will review some of the conditions under which RDC occurs and propose some ways to deal with the problems that occur up front in the design phase.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related White Papers
- SoC tool flow techniques for detecting reset domain crossing problems
- Understanding Clock Domain Crossing Issues
- Clock Domain Crossing Glitch Detection Using Formal Verification
- The Challenge of the Clock Domain Crossing verification in DO-254
Latest White Papers
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- The pivotal role power management IP plays in chip design
- What tamper detection IP brings to SoC designs
- Analyzing Modern NVIDIA GPU cores
- RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware