Reuse UVM RTL verification tests for gate level simulation

David Vincenzoni, STMicroelectronics
EDN (October 01, 2015)

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible corner cases to minimize verification time. A mix of several techniques and methodologies are used to improve the functional verification and extract a measure of the grade of coverage: Formal verification and random constrained tests based on Universal Verification Methodology (UVM) increase the probability to discover bugs. Sometimes we create a perfect and effective test for RTL verification only to find out it can’t be reused during the gate level simulation because the UVM Monitors are hooked on internal SoC signals that can disappear or change after the implementation phase.

This article will describe how easy it is to create efficient self-checking tests that are straightforward, and reusable during gate level simulations. It is surprising that, by changing the data flow, we can have benefits for the test bench, reducing the complexity of scoreboards, which also means less time for test developing.

The flow is based on the instantiation of UVM Verification Components used for checking interfaces such as SPI, I²C, & UART, but it can also be extended for more complex interfaces.

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