Productivity Boost in Embedded Processor Design
by Rainer Leupers, Tim Kogel, Heinrich Meyr, Andreas Hoffmann, Uri Mayer,Steffen Buch and Mario Steinert
Increased flexibility and efficiency are requirements of embedded processors (EPs) for today's complex SoC designs. This article addresses traditional methodologies that are used in EP design, and some challenges designers are facing today. It will also describe new methodologies and technologies that are emerging to dramatically shorten the embedded processor design cycle.
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related White Papers
- Emerging Trends and Challenges in Embedded System Design
- The role of cache in AI processor design
- How to boost verification productivity
- Standard design constraints: The next productivity boost for custom design
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience