Productivity Boost in Embedded Processor Design
by Rainer Leupers, Tim Kogel, Heinrich Meyr, Andreas Hoffmann, Uri Mayer,Steffen Buch and Mario Steinert
Increased flexibility and efficiency are requirements of embedded processors (EPs) for today's complex SoC designs. This article addresses traditional methodologies that are used in EP design, and some challenges designers are facing today. It will also describe new methodologies and technologies that are emerging to dramatically shorten the embedded processor design cycle.
Related Semiconductor IP
- USB 20Gbps Device Controller
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
- Bluetooth Low Energy Subsystem IP
- Multi-core capable 64-bit RISC-V CPU with vector extensions
Related White Papers
- Emerging Trends and Challenges in Embedded System Design
- The role of cache in AI processor design
- How to boost verification productivity
- Standard design constraints: The next productivity boost for custom design
Latest White Papers
- CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systems
- On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs