Predicting PLL reference spur levels due to leakage current
Michel Azarian, Sr. Applications Engineer, and Will Ezell, Mixed Signal Products, Linear Technology
EETimes (11/9/2012 12:22 PM EST)
A simple model can be used to accurately predict the level of reference spurs due to charge pump and/or op-amp leakage current in a phased-locked loop system. Knowing how to predict these levels helps pick loop parameters wisely during the early stages of a PLL system design.
Quick review of PLLs
The phase-locked loop (PLL) is a negative feedback system that locks the phase and frequency of a higher frequency device (usually a voltage controlled oscillator (VCO) whose phase and frequency are not very stable over temperature and time to a more stable and lower frequency device (usually a temperature compensated or oven-controlled crystal oscillator, (TCXO or OCXO). As a black box, the PLL can be viewed as a frequency multiplier.
To read the full article, click here
Related Semiconductor IP
Related White Papers
- Keeping leakage current under control
- Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
- Chip recovery has started, says analyst predicting 10% growth in 2001
- Memory overwhelms current verification techniques
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience