PLL

Block Diagram

PLL Block Diagram

Deliverables

  • Our analog IPs include ADC, DAC, PLL, LDO, POR and more, available for 28~65nm fabrications in different foundries like GF, SMIC, TSMC, HHGrace, and UMC. We can also customize porting IPs for customers requiring 65~180nm fabrications and support more advanced processes as needed.

Technical Specifications

Foundry, Node
SMIC,40,55,65; GF,28,55; HHGrace,55
Maturity
Silicon Proven
Availability
Immediate
GLOBALFOUNDRIES
Silicon Proven: 28nm , 55nm
SMIC
Pre-Silicon: 40nm LL
Silicon Proven: 65nm LL
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Semiconductor IP