Migration path laid to low-cost 32-bit MCUs

Haydn Povey
(12/06/2004 10:00 AM EST)

Traditionally, low-end 8-bit and 16-bit devices have served the microcontroller market, an arena marked by limited functional requirements and a highly cost-sensitive user base. But as application requirements evolve and industries look to consolidate multiple MCUs into single devices, organizations are focusing on how they can migrate to an affordable 32-bit platform.

Aided by the advent of many new technologies, it now appears certain that 32-bit microcontrollers will become available across the cost range traditionally held by 16-bit and high-end 8-bit MCUs.

The wealth of MCU applications means new microprocessor architecture cores must be synthesizable and available. Additionally, the number of applications requires that the microprocessor architecture must be open, to enable silicon vendors to integrate the peripherals they need as opposed to those set by the microprocessor provider.

The challenge is to enable a 32-bit microprocessor core at the cost standards of the 16-bit market. The cost to manufacture a microcontroller is mostly determined by the packaging. So to reduce the cost of producing a 32-bit microcontroller, the industry should look at how it can use older, less-expensive manufacturing processes, such as 0.35, 0.25 and 0.18 micron; how it can reduce the size of the microcontroller to minimize silicon area; and how it can eradicate superfluous pins, especially for sub-50-pin packages.

Typically the largest standard components of a microcontroller are the flash memory, used for instruction storage, and SRAM, used for data storage. To minimize physical area, the industry needs to look at how it can facilitate end users' making better use of these resources. That, in turn, will enable a smaller package, allowing the use of an older, cheaper process technology.

Optimizing the flash memory itself is possible by using next-generation 32-bit instruction-set architectures to deliver far higher code density and thus optimize the amount of flash required to achieve a specific task.

Optimizing the SRAM is a matter of how the microprocessor orders and stores the data inside the memory. Techniques include unaligned data support, which enables the processor to store multiple data types next to each other. Bit banding can also be used. That allows the programmer to manipulate single bits of memory with no processing overhead, ensuring 100 percent memory utilization in applications that require the storage and manipulation of unitary data, such as the status of a flag, switch or LED.

It is also possible to reduce the cost of 32-bit devices by applying new techniques to the implementation of the main processor core. In addition, the tight integration of certain closed system peripherals, such as the bus matrix, interrupt controller and debug features, can reduce the overall system gate count and hence the silicon area required. Other, more specific features can be integrated on the board, including hardware division and single-cycle multiply. These two features have been shown to reduce the gate count by more than 30 percent.

Similarly, the implementation of a very closely coupled interrupt controller has reduced the gate count required over a generic controller and has enabled a halving of the number of cycles taken to enter an interrupt, as well as a massive, 85 percent reduction in the number of cycles to move between pending interrupts. This is especially crucial in the realm of control.

Peripherals are arguably the most important component of the microcontroller. However, it is surprising to some that these could offer the largest physical area savings to produce a lower-cost 32-bit device. On close inspection of many common peripherals provided on 8- and 16-bit microcontrollers, it is clear that many of the blocks include lots of additional circuitry to make up for limitations in the microprocessor: deep FIFOs, for example, and extra sets of registers on UARTs and additional interpolation circuitry on digital-to-analog converters. The movement to higher-performance 32-bit controllers removes the need for most of this "hidden" circuitry, enabling much smaller peripherals. For example, the wider bus architecture enables the swifter movement of data to and from communication ports, and the increased processing power of the core removes the need for external interpolation.

All 32-bit microcontrollers have far better debug than traditional 8- and 16-bit microcontrollers. Nevertheless this huge advance in system visibility and ease of debug comes at the cost of a five-pin overhead to support a JTAG debugging port. While the overhead is not an issue for devices with higher pin counts, such as more than 50 pins, it certainly poses issues for devices at the lower end of the market that may only have 20 pins or less. There, the overhead represents potentially 25 percent of total pins and thus an increase of 25 percent in packaging costs.

To build 32-bit microcontrollers that cost less than $1, processor designers have been investigating new ways to tap the on-chip debug information less intrusively. One example of this is the single-wire debug port, which enables microcontroller designers to deliver all of the functionality of JTAG on one pin (in addition to or in replacement of a traditional JTAG port).

Haydn Povey (haydn.povey@arm.com) is the MCU product manager for ARM (Sunnyvale, Calif.).