Select the Right Microcontroller IP for Your High-Integrity SoCs
By Enrique Martinez-Asensio, Ensilica
ElectronicDesign (June 25, 2024)
It seems like there’s an almost unlimited array of microcontrollers—from low-cost 8-bit varieties to high-performance 32/64 multicore systems. While some systems require little thought beyond cost or speed, there are also many high integrity applications requiring reliability, security and/or functional-safety (FuSa) standards to be met, requiring the architect to pay special attention to the MCU selection.
At the extreme end, today’s vehicles contain 100+ MCUs serving different functionalities: infotainment, steering, braking, engine control, ADAS, etc. Some of these systems are built with commercially available MCUs. However, when a high degree of integration and low cost are the top priorities, dedicated systems-on-chips (SoCs) become necessary. These contain not only an MCU but additional analog/digital processing functionalities.
This article runs down seven of the considerations that we use when selecting an MCU IP for a high-integrity ASIC or SoC. We also look at several of the IPs available on the market.
To read the full article, click here
Related Semiconductor IP
- Microcontroller
- 32-bit RISC-V microcontroller
- 1.65V Low Noise Microphone Bias for Microcontroller Business in TSMC 55nm
- 12-bit, 6MS/s ADC for Microcontroller Business in Samsung LFR6LP
- 12-bit, 2MS/s SAR ADC IP for Microcontroller Business in TSMC 55nm
Related White Papers
- Embedded Systems -> Microcontroller designers eye Internet access
- Microcontroller Applications -> 'Internetworking' treads on MCU turf
- Microcontroller Applications -> PLD solution takes on microcontroller
- Microcontroller Applications -> Connectivity invigorates MCU designs
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience