IP Integration - Size Matters! - Reducing the size of a USB 2.0 device core
By Tom Halfhill, ARC International
Embedded System Engineering
www.esemagazine.co.uk
How a System Perspective Slashes the Size of a USB 2.0 Device Core
USB 2.0 is a dramatic improvement over USB 1.1. Among other things, it’s 40 times faster and has new flow-control features that use bus bandwidth more efficiently. Yet it’s fully backward-compatible with existing USB 1.1 products. This combination of higher performance and broad compatibility almost guarantees that USB 2.0 will succeed in the marketplace -- a market that has already embraced USB 1.1 in personal computers, peripherals, digital cameras, industrial equipment, and many other applications.
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related White Papers
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
- Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment
- SOC Stability in a Small Package
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening