How to use FPGAs to implement high-speed RLDRAM II interfaces

Increasing I/O bandwidth requirements in the graphics, telecom, and communication industries and growing PC processor speeds are fueling a need for high performance memory interfaces. This "How To" article focuses on RLDRAM II technology and the implementation of a high-speed interface in programmable logic. Techniques are identified that a programmable logic memory controller designer should implement to overcome these barriers. In particular, a case is presented for using embedded silicon approaches in programmable logic for automatic alignment of data strobes to data during the READ and WRITE cycles.

The market need for RLDRAM II
To keep up with the growing industry needs, system designers migrated from single data rate (SDR) SDRAM memory to double data rate (DDR) SDRAM and further to DDR2 SDRAM memory devices. Memory access latency, however, has become a huge bottleneck for communication and networking applications. Reduced Latency DRAM I (RLDRAM I) has evolved to fulfill requirements of these applications. Reduced Latency DRAM II (RLDRAM II) memory combines the networking and cache required by applications such as high density (256Mb), high bandwidth (2.4Gbps), and fast SRAM-like random access times.

RLDRAM II interface overview
RLDRAM II uses a DDR scheme, performing two data transfers per clock. RLDRAM II devices use either the 1.5V HSTL or 1.8V HSTL class I/II I/O standards. Each RLDRAM II device is divided into eight banks, where each bank has a fixed number of rows and columns. WRITE and READ operations are burst oriented and all the bus width configurations of RLDRAM II support burst lengths of 2, 4, and 8 bits. In addition, RLDRAM II devices support bus width configurations of ×9, ×18, and ×36.

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