How to reduce costs by integrating PCI interface functions into CPLDs

Expansion buses are connections that allow peripheral controllers to use system resources, such as hard disks, memory and I/O space, and audio/video hardware. The most commonly used expansion bus in today's systems, the peripheral component interconnect (PCI) bus, provides a shared data path between the CPU and peripheral controllers in computers ranging from laptops to mainframes. The PCI bus was originally developed by Intel in the early 1990s for its Pentium family processors, but it is also widely used with legacy 486 family processors as well as with more modern processors.

Today, the PCI is a standardized, highly efficient expansion bus supported by several computer platforms, including PC-compatible computers, PowerPC-based platforms, and so forth. PCI originally operated at 33 MHz using a 32-bit-wide path. Over time, several revisions were made to the PCI standard, including increasing the speed from 33 MHz to 66 MHz and doubling the width of the bus to 64-bits. A typical PCI local bus system architecture is illustrated in Fig 1.

Many of today's PCI bus interfaces are implemented using application-specific standard products (ASSPs). Nevertheless, designers still face the challenge of reducing board space, flexibility, obsolescence, and total system cost.

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